6.0 Computer Memory
6.01 Location:
6.011 internal
6.0111 Main Memory
6.0112 Registers: Processor Local Memory
6.0113 Control Unit Memory
6.0114 Cache
6.012 external
6.0121 Peripheral Storage Devices
6.01212 Tapes and Disks
6.0122 Availble through I/O controllers
6.02 Capacity:
6.021 Bits
6.022 Bytes
6.023 Words (8,16,32 and 64 bits)
6.03 Units of Tranfer:
6.031 Equal to the number of lines in and out of the memory device
6.032 May be equal to a word or larger (64, 128, 256)
6.033 Main Memory: The Number of bits read/write into
memory at a single time.
6.034 External: Often transfered in units larger than a
word, such as a block.
6.04 Addressable Units: Usually a Word size but some units
allow for Byte Size addressing
6.041 The relationship between length in bits A of an
address and the number of addressable units:
2A = N <==============================What?
6.1 Memory Access:
6.11 Methods:
Sequential
Direct
Random
Associative
6.12 Sequenction Access:
.121 Memory organzed into Record Units
.122 Access is linear
.123 Addressing Information is stored to make
Record Accessing easier
.124 Shared Read/Write Mechanism is used
.125 Access requires moving through records to
fnd what you want to use for R/W
.126 Example: Backup Tapes
6.13 Direct Access:
.131 Shared Access (R/W) mechanism (similar to
sequntial)
.132 Block or Records have unique Addresses
based on physical location
.133 Direct Acces to the area of the storage and
then sequential counting to find the exact data
location
.134 Variable Access Time
.135 Example: Disk Units
6.14 Random Access:
.141 Each Memory Unit has a specific, unique, wired address
.142 Time to access each location is independent
of previous memory access and access is fairly
constant
.143 Example: Main Memory and certain cache.
6.15 Associative Access:
.151 A type of random access
.152 enables one to make a comparison of desired bit
locations within a word for a specified match
.153 Does this for all Words simulatenously
.154 A word is retrieved based on its content,
rather than its address.
.155 Retrieval Time contastant - Each location
has its own addressing location
.156 Examples: Some Cache memories
6.2 Memory Charactoristics:
6.21 Capacity
6.22 Performance
.221 Access Time: The Time it takes to perform
an individual R/W
.222 Memory Cycle Time: System Bus dependent
time where the a R/W cn start after one
completes.
.2221 Most a Random Access Memory Issue
.223 Transfer Rate: The rate in which data can
transfer in and out of a memory unit
6.3 Physical Memory Types:
6.31 Semiconductor
.311 Volatile or NonVolatile
6.32 Magnetic Surface
.321 NonVolatile
6.33 Optical
6.34 Magneto-Optical
6.35 Memory Physical Properties:
6.351 Volatile: Leaks Memory and Disapates when
powered down.
6.352 NonVolatile: Memory remains once stored
until deliberately changed
6.353 Nonerasable: ROM in Semiconductor Material
6.354 Organization Design - Especially for RAM
is essential to its use and description. How
the bits and words are translated in physical
memory.
6.4 Memory Heirachy: Traditional memory design where the
fastest and most expensive form of memory is close to the
processor and less expensive and larger memory resources are
further off the system core.
6.41 Locality of reference: The theory that areas of
memory, over the short period of time, is more intensly
used than outside clusters of memory. This gives
advantage to a system of memory movement where the
system cashes clusters of memory for processing usage.
6.42 Inboard Memory:
6.421 Registers, Cache, Main Memory
6.43 Outboard Storage:
6.431 Magnetic Disk, Optical Disks, etc
6.44 Offline Storage:
6.441 BAckup Tapes
Heirarchy
-----------
Register
Cache
Main Memory
Magnetic Disk
Tape
6.5 Memory Caching Technique
CPU <====> Cache <====> Main Memory
fast slow
CPU <==> L1 <==> L2 <==> L3 <==> Main Memory
Fastest Fast Less Slow
Fast
6.51 Each Cache location would have a numer of memory
words at a single location.
6.511 Processor generates a read address
6.512 Check if the address is in the block
contained in the cache.
.5121 If it is in the cache block,
return the data for the address
.51212 If that address is not in any of
the blocks in the cache, retrieve the
block with the address. The cache then
send the data on to the CPU
.51213 Alternatively, the Data and
Address lines can be connected from the
CPU to the Main Memory and the Cache in
parallel. This gives the advantage that
when you have a cache miss, the cache
can call for the memory and it enters
the cache and the CPU registers
simultaneously.
http://www.nylxs.com/docs/grad_school/arch/cache_memory_parellel.png
.512131 Parallel Control
When a memory address is listed in the
cache in a parallel architecture, then
the cache, which has the control line
between the system bus and the
processor, turns off access to the
system bus, preventing traffic on the
bus.
6.52 Elements of Cache Design:
6.521 Addressing: Logical or Physical
6.5211 Virtual Memory -
Hardware Memory Management
Module translates virtual
addresses for real physical
address.
6.52111 MMU - Memory
Management Unit: Can
sit between cache and
the processor or between
cache and the system
bus.
6.52112 Logical
Addressing: Cache is
between the and the MMU
521121: No MMU access for cache
hits (good)
521122: Addresses not unique
and therefor, the cache must be
flushed clean between
application switches or extra
bits need to be added to the
address to specify the virtual
process running the virtual
memory
6.522 Cache Size
6.523 Mapping Function:
The Memory is larger than the
cache so in order to reach all
memory locations, an algorithm
must be constructed
.5231 Direct - Maps each memory
address to a single possible
cache line.
http://www.nylxs.com/docs/grad_school/arch/direct_cache_model.png
.5232 Associative -
21 Any Memory
block can be
assigned to any
cache line
22 An address is
interpreted as a TAG or
WORD field
23 Every line is looked
for a matching tag as
the currently requested memory
address in order to
determine if it is in
the cache or not
.5233 Set Associative - A little bit of
each of the above in an effort
to reduce their disadvantages.
.5234 Set Associative
6.524 Replacement Algorithm
.5241 Least Recently Used (LRU)
.5242 First in First Out (FIFO)
.5243 Least Frequently Used
(LFU)
.5244 Random
6.525 Write Policy
.5251 Write Through
.5252 Write Back
6.526 Line Size
6.527 Number of caches and their
relationship:
.5271 Single or Two Level
.5272 Unified or Split